Introduction: transistors. Architecture of 8086: 8086 microprocessor is


Microprocessors do not have inbuilt memory. 8086
microprocessor was designed and invented by Intel in 1976. It’s a 16-bit
Microprocessor having 20 bit address lines and 16 bit data lines that are
multiplexed (AD0-AD15).

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Words will be stored in two consecutive memory
locations. If the first byte of the word is at an odd address, the 8086 will
read the first byte in one operation and the second byte in another. Else if
the first byte of word is at even address, the 8086 can read the entire word in
an operation.


It has faster processing as it has an
instruction queue capable of storing six instruction bytes from the memory.

Faster processing is also due to 16-bit
ALU, 16-bit registers, internal data bus, and 16-bit external data bus. It was
the first 16-bit processor with such features.

Performance is improved by pipelining.
Pipelining has two stages, i.e. Fetch Stage and Execute Stage. Fetch stage
stores up to 6 bytes of instructions in queue, while execute stage executes

It has large number of transistors,
approximately 29,000 transistors.

of 8086:

8086 microprocessor is divided into two functional

1.      Execution
Unit (EU)

2.      Bus
Interface Unit (BIU).

Unit (EU)-

This unit commands BIU starting from where to fetch
the data and then decode and execute those instructions through giving
instruction. By using instruction decoder and ALU, it controls operations on

Some functional part of 8086 microprocessor are:

1.      ALU-
It handles arithmetic and logical operations.

2.      Flag
Register- 16-bit register which changes it status according to the result
stored in the accumulator. There are in total 9 flags. They are divided into 2
groups – Condition Flags and Control Flags.

3.      Status
Flags- It represents the result of the last instruction executed.

a.       Carry
Flag: This will indicate the final carry of the instruction.

b.      Auxiliary
Flag: This will represent the in between carries generated by the instruction

c.       Parity
Flag: It will show the whether number of 1’s is odd or even in the result.

d.      Zero
Flag: If the result of the operation is zero, then the flag will be set to 1
else 0.

e.       Sign
Flag: When the result of the operation is negative, then the flag is set to 1 else
set to 0.

f.       Overflow
Flag: This will indicate the result when the capacity of the system is

4.      Control
Flags- It controls the operation of the EU.

a.       Trap
Flag: For debugging, it allows the user to execute one instruction at a time
and is used for single step control.

b.      Interrupt
Flag: It allows/prohibits interruption of a program. To enable the interruption,
it is set to 1 else set to 0 for interrupt disabled.

c.       Direction
Flag: If is used for the string operation. If the pointer is pointed at the
last character of the string, then the flag is set to 1 and the pointer will be
decremented. If the pointer is pointing to the first character of the string,
then the flag is set to 0 and will be incremented.

5.      General
Purpose Registers- There are 8 general purpose registers, namely, AH, AL, BH,
BL, CH, CL, DH, and DL. These can be used individually to store 8-bit data and
can be stored as 16-bit by making pairs. It is referred to the AX, BX, CX, and
DX respectively.

a.       Accumulator
register (AX) – Used to store operand for arithmetic operations.

b.      Base
register (BX) – Used to store the starting bas address of the memory area.

c.       Counter
(CX) – Used in loop instruction to store the loop counter.

d.      Data
register (DX) – Used to hold I/O port address for I/O instruction.

6.      Stack
Pointer Register- It holds the address from the start of the segment to the
memory location.

Interface Unit (BIU):

It takes care of all the data and addresses transferred
on the buses for the EU, EU has no direct connection with System Buses so it is
possible with the BIU. Both the units are connected with the internal buses.

BIU has following functional parts-

1.      Instruction
queue- Up to 6 bytes of next instruction is given to BIU which stores them in
the instruction queue. When EU is ready to fetch the next instruction, it
simply reads it from the instruction queue resulting in execution speed.
Fetching the next instruction before the current execution is completed is
called as Pipelining.

2.      Segment
register- Bus Interface Unit has 4 segment buses, i.e. CS, DS, SS, and ES.

a.       Code
Segment (CS) – It addresses the memory location in the code segment of the

b.      Data
Segment (DS) – Consist of data used by the program and is accessed in the DS by
an offset address.

c.       Stack
Segment (SS) – Handles memory to store data and addresses.

d.      Extra
Segment (ES) – It is additional data segment used by the string to hold the
extra destination data.

3.      Instruction
Pointer- This pointer holds the address of the next instruction to be executed.


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